The present invention relates generally to the field of integrated circuits and their operation, and more specifically to devices known in the industry as programmable logic devices. In particular, one embodiment of the present invention provides a programmable logic device with enhancements for efficient implementation of a first-in, first-out (FIFO) memory device.
Programmable logic devices have found particularly wide application in the industry. Their versatility, low design cost, and ease of use have combined to make these devices widely used in the logic design process. Programmable logic devices (sometimes referred to as PLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, or FPGAs,) are well known integrated circuits that combine the advantages of fixed integrated circuits with the flexibility of custom-designed integrated circuits.
The distinguishing feature of a programmable logic device is the ability of a user to electronically program a standard, off-the-shelf part to perform logic functions to meet the user's individual needs. Their use is well-known in the industry and are described, for example, in U.S. Pat. No. 4,617,479, which is incorporated herein by reference for all purposes. Such devices are currently represented, for example, by Altera's MAX.RTM. series of PLDs and Altera's FLEX.RTM. series of embedded PLDs.
A technique by which programmable logic devices have been implemented uses multiple blocks of configurable logic which are interconnected by some type of interconnection system. These configurable logic blocks are electronically programmable to provide desired logic functions. In order to provide efficient implementation of different functions, the configurable logic blocks are sometimes specially designed for certain applications. For example, one type of configurable logic block is a logic array block (LAB). LABs are designed to be useful in implementing generalized logic functions. Another type is an embedded array block (EAB). EABs are specially designed for implementing memories and other specialized logic functions. Often, different types of configurable logic blocks are provided within a single programmable logic device. This gives a user flexibility in realizing desired logic functions.
The configurable logic blocks are typically coupled together by an interconnection system. For example, a popular programmable logic device provides an interconnect grid to connect different configurable logic blocks to each other and also to input/output ports. This interconnect grid typically comprises sets of horizontal conductors and vertical conductors which are programmably connected to the configurable logic blocks and the input/output ports.
In addition to the interconnect grid, often each of the configurable logic blocks have local interconnect systems. These local interconnects are conductors which provide either fixed or programmable routing of signals within the configurable logic block.
Altera's FLEX.RTM. 10K line is an example of a product that provides both logic array blocks and embedded array blocks in a single programmable logic device. The embedded array blocks and logic array blocks are coupled by an innovative interconnect system. The FLEX.RTM. 10K line is described, for example, in the Altera Data Book, June 1996 and U.S. Pat. Nos. 5,241,224 and 4,871,930, which are included herein by reference for all purposes.
A common application for which a programmable logic device may be used is a first in, first-out (FIFO) memory. A FIFO is a particular memory scheme in which data is read out from the memory in the same order in which it was written into the memory. As is well known in the art, the implementation of such a device may include, for example, two counters and a memory array. One of the counters is a pointer to the next address from which data is to be read, while the second counter is a pointer to the next address to which data is to be written.
According to the present state of the art, multiple configurable logic blocks are used to design such a FIFO in a programmable logic device. Typically, for example, the counters are implemented in a logic array block or other configurable logic block. The memory array is implemented in a second configurable logic block, for example, an embedded array block. In such an arrangement, two sets of address lines are routed from the counters in the logic array block to the memory array in the embedded array block.
Routing of signals throughout a programmable logic device is a significant issue. Often, the number of available conductors is limited. The space required for introducing more conductors is significant. In a generalized device such as a programmable logic device, it is particularly desirable that the number of interconnections be as low as possible, while still allowing the user to implement common functions. By keeping the number of interconnections at a minimum, more of the space is available for implementing logic functions.
It is apparent from the above, that an improved programmable logic device is desirable. The present invention recognizes the desirability of implementing a FIFO memory in a programmable logic device while saving the number of conductors of the interconnect system that must be utilized.